Balancing the cost of test and board density
It is always a challenge for test engineers to balance the cost of tests to maintain competitiveness and achieve optimal test coverage of the product. In many cases, gaining conventional 100% test access is no longer applicable. Test engineers are exploring limited test access solutions to lower the cost of tests with new paradigms in ICT to avoid increasing board density.
Implementing a 100% test point access strategy is difficult, even when high product margins could absorb the testing costs. This is particularly true for high-speed differential signaling boards, where test points are often not permitted. As board testing becomes more expensive, businesses may view it as an unnecessary expense rather than a valuable investment.
So, why perform PCB assembly testing?
The answer has two key points. First, manufacturers cannot ensure product quality without proper testing. Second, when testing is done correctly, it saves companies time and money. Inadequate testing can lead to substandard products reaching customers, resulting in warranty claims, costly repairs, replacements, and a damaged brand reputation. In some industries, it may even expose companies to potential lawsuits.
Conversely, adequate testing does not mean 100% test coverage. Achieving near-perfect coverage is not only unnecessary but also prohibitively expensive. The costs associated with chasing the final few percentage points can drive up both production expenses and the product retail price exponentially.
It is crucial to determine the optimal level of testing for a specific product and the industry it serves, to ensure its quality while managing testing costs. For instance, military and aerospace products demand a much higher investment in testing due to their mission-critical nature. On the other end of the spectrum, lower-cost consumer electronics can tolerate a certain level of product defects without the need for extensive testing.
Finding optimum testing coverage
Testing a PCB assembly involves evaluating three key elements: structural devices, structural connections, and functional connections. These are examined using a blend of widely used visual, electrical, and functional testing techniques. Methods include automated optical inspection (AOI), automated X-ray inspection (AXI), in-circuit testing (ICT), boundary-scan, and custom test software.
Many PCB assembly manufacturers use boundary-scan testing to provide comprehensive coverage for board testing. Boundary-scan testing is more cost-effective than standard PCB testing methods like in-circuit testing (ICT). While both methods involve expenses for equipment acquisition, procedure development, training, and labor, ICT also requires the additional costs of developing test fixtures and maintaining equipment—expenses that can be avoided with boundary-scan testing.
Boundary-scan: What is it?
Boundary-scan is a technique for testing interconnects on PCBs without the need for physical test probes. It utilizes a standard test access port (TAP) and boundary-scan cells to control and monitor the state of each pin on a device. Boundary-scan is essential for modern PCB testing, as it enables comprehensive testing of complex boards with high component density and limited test access.
Testing with in-circuit testing (ICT) requires test access, which refers to the test points—typically pads or vias—designed into the PCB that allow probes to provide the electrical connections between the board under test and the tester. Without the test points on the trace, engineers may turn to limited access solutions, such as the IEEE 1149 standard for boundary-scan testing which provides a guideline on differential signal boundary-scan interconnect testing.
A boundary-scan test enables the manufacturer to check a board’s functionality without full access to its internal circuitry to ensure accurate and reliable testing. The prerequisite is that the manufacturer needs to design the boards according to the IEEE 1149 standard, which requires boundary test cells connected to each pin. Using IEEE 1149 standard information, the manufacturer can easily verify the overall functionality of a PCBA without needing to check on its components.
Unlike other testing methods that require expensive test equipment, the boundary-scan technique relies on logic and uses minimal testing tools and is less costly and more effective. Also, the technique does not require a lot of physical access and will perform comprehensive testing as long as the circuit is designed according to the boundary scan standard.
How does the boundary-scan test work?
The tester sends diagnostic signals to the device’s test data input (TDI) pin in a typical boundary-scan test. The boundary-scan cells capture the signals and serially shift them through the core logic that scans them. The output is then serially shifted out of the core through the test data output (TDO) pin, as shown in Figure 1.
Figure 1 IEEE 1149.1 Boundary scan testing
The last step involves comparing the output with the expected result and consequently identifying if there are shorts, opens, missing devices, dead components, and internal defects within components, as shown in Figure 2.
Usually, the boundary-scan technique enables engineers to configure the cells in two main testing modes. This includes the internal testing mode to check the logic inside the chip, while the external mode tests the interconnects between the ICs on the PCB.
Figure 2 Output compared with the expected result.
How does a boundary-scan help to maximize test coverage?
When it comes to testing electronic boards, achieving optimal test coverage is essential for ensuring product quality and reliability. Boundary-scan allows for comprehensive testing of digital components and interconnections on a board, including those that are difficult to access through traditional methods. By using specialized boundary-scan tools and techniques, engineers can identify test coverage gaps and improve the overall testing strategy.
One technique for identifying test coverage gaps is through fault simulation. By simulating different fault scenarios, you can analyze the effectiveness of your test vectors and identify areas where additional coverage is needed. This helps in designing more effective test patterns that can detect faults that might have been missed using traditional testing methods.
Another way to maximize test coverage is by utilizing boundary-scan in combination with other testing methods. Boundary-scan can complement functional testing, in-circuit testing, and other techniques to provide a more comprehensive assessment of a board’s functionality. By combining these methods, you can increase the probability of detecting faults and improve the overall reliability of your product.
Real-world case studies have demonstrated the effectiveness of boundary-scan in improving test coverage. For example, a manufacturer of automotive electronics was able to identify and fix a critical fault in a complex circuit that was previously undetected using traditional testing methods. By incorporating boundary-scan into their testing process, they were able to achieve higher test coverage and ensure the quality and safety of their products
How to integrate boundary scan testing capability into an in-circuit tester?
Manufacturing testing that relies on traditional in-circuit testers without boundary-scan capabilities faces challenges on loss of physical access to fine pitch components, such as surface mount technology (SMTs) and ball grid array (BGA), reduces bed-of-nails ICT fault isolation. Development of test fixtures for ICTs becomes more expensive, and test procedures for ICTs become longer and more expensive due to more complex ICs. Designers are forced to bring out a large number of test points, which is in direct conflict to miniaturize the design. Also, in-system programming is inherently slow, inefficient, and expensive if done with an ICT.
Integrating a boundary-scan into the ICT enables concurrently performing a boundary-scan test and an in-circuit test (ICT). This eliminates the need for separate testing stations for the server board’s central processing unit (CPU) and Dual In-line Memory Module (DIMM).
Figure 3 Boundary scan connection to i3070 Series 7i in-line ICT system
Figure 3 shows the boundary-scan connection method to the Keysight i3070 Series 7i in-line ICT system. In this setup, a ribbon cable connects to the test interface fixture (TIF). The connection extends from the TIF to the fixture probe via T-Pins, reaching the joint test action group (JTAG) header, which is not on the unit under test (UUT). This method enhances signal integrity because the JTAG header is mounted directly on the test PCB, closer to the device under test. This proximity reduces resistance and impedance, preventing signal degradation. Additionally, the boundary-scan x1149 controller is now enclosed within the test head.
Boundary-scan is shaping the future of manufacturing testing
Boundary-scan is a powerful technique for enhancing the test coverage of PCBs. By providing access to hidden nodes, enabling non-intrusive testing, and integrating with other test methods, it offers a comprehensive solution for modern electronics manufacturing. While there are challenges in implementation, the benefits of improved reliability and efficiency make it a valuable addition to any PCB test strategy. The Keysight x1149 boundary scan analyzer is a comprehensive and versatile board test solution that provides everything you need to efficiently test and analyze circuit boards during every stage of the development process. Whether in the research and development phase or preparing for production, the Keysight x1149 boundary scan analyzer makes it easy to design, analyze, and test your circuit boards with its coherent software interface. The Keysight x1149 software revision 2.0 provides a more robust, user-friendly testing environment and performance enhancement. It enables users to streamline testing processes, save time, and achieve more accurate and reliable results, making it an essential tool for testing complex electronic systems.
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