Semiconductor IP Management Strategies to Accelerate Design Flows

Key takeaways:

• As integrated circuits (ICs) grow more complex, semiconductor IP management becomes critical for faster time-to-market while enhancing the design performance.
• Semiconductor IP can be categorized based on hard vs. soft cores, functionalities, sources, and development methodologies.
• System-on-a-Chip (SoC) design evolves from monolithic single-die to chiplet-based, multi-die systems, demanding IP traceability from inception through integration.

The integration of semiconductor intellectual property (IP) blocks into complex integrated circuit (IC) designs presents many demanding challenges. Modern IC design teams, often distributed across different countries, must collaborate to navigate multi-tool design flows and a frequent shortage of expertise in semiconductor IP that were not developed locally. Additionally, the shift towards chiplet-based designs and the pressure of adhering to strict regulations like export controls demand rigorous traceability and effective management of both internal and third-party IPs (Intellectual Properties).

This article delves into the world of semiconductor IP, how to categorize IP, challenges and trends in managing these vital assets throughout their lifecycle, implications of chiplet on IP management, and crucial strategies for streamlining semiconductor IP management.

What is semiconductor IP?

Semiconductor IP blocks, or IP cores, are foundational elements in the design of systems-on-chip (SoC) and integrated circuits (ICs). These pre-designed and pre-verified design components streamline development by enabling the reuse of existing functional elements, thus speeding up design processes and allowing designers to concentrate on innovative product differentiation.

Figure 1. Block diagram of an SoC with its IP blocks

IP cores vary in complexity depending on specific design requirements. As shown in Figure 1, within the SoC, simple IP blocks include memory and peripheral subsystems like the Universal Serial Bus (USB). More complex IP blocks, often developed by specialized companies, include main processor cores such as the GPU and CPU. Effective management of these IPs is crucial. Tools like Keysight IP Management (HUB) play an essential role in cataloging, tracking, sharing, and securing these valuable assets.

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A brief history of semiconductor IP

The history of semiconductor Intellectual Property (IP) reflects pivotal shifts to modular-based design methodologies that have democratized chip design and shaped the electronic design industry over decades.

The 1980s: early development of design libraries

The advent of Computer-Aided Design (CAD) tools in the 1980s ushered in a new era of sophistication in chip development. For increasingly complex and integrated SoCs, it became virtually impossible (unaffordable) for smaller companies to develop all the necessary blocks on its o own. As a result, SoC developers gan to recognize the value of sharing and licensing previous design elements, the original silicon IP cores, to reduce development costs.

The 1990s: the rise of silicon IP markets

The 1990s saw an explosion of growth in the electronics industry, fueled by sectors like wireless phones, gaming consoles, and personal computers. This boom drove semiconductor design companies to shorten their time to market and shift to new process nodes more swiftly through IP reuse. ASIC companies created “content,” leading to early IP companies. With increasing demand for IP, the second half of this decade was characterized by the emergence of multiple third-party IP vendors such as Artisan Components and Virage Logic.

The 2000s: consolidation and integration

What started with simple RTL (register transfer level) data has significantly evolved, now incorporating a suite of complex functionalities that include both analog and digital components, verification suites, synthesis scripts, and more. More complex IP cores can cost from hundreds of thousands to millions of dollars.

Standards such as AMBA have been developed to facilitate seamless IP integration. Moreover, the semiconductor IP landscape has seen considerable consolidation, with industry giants like ARM, Synopsys, and Cadence acquiring smaller IP providers to expand their portfolios.

Types of semiconductor IP

Semiconductor IP cores are categorized in different ways based on technical and business characteristics. Below are some of the common organizational schemes.

Hard vs. soft IP cores

Figure 2. Type of IP cores: hard vs. soft

Hard IP cores

Hard IP cores are delivered as specific physical implementations tailored to a particular chip fabrication process, often aligned with a specific foundry’s requirements. These cores are already synthesized, placed, and routed. Common hard IP cores include memory controllers (e.g., DDR) and analog or mixed-signal IP blocks.

Features of hard IP cores:

• Physical specification formats: Hard IPs are provided as ready-to-use transistor-layout formats.
• Process-specific designs: These cores are optimized for a particular foundry’s process, focusing on performance, power, and area efficiency within that specific fabrication methodology.
• Fixed functionality: Hard IP cores are designed for specific functions or tasks and cannot be easily modified or customized. They also require little to no additional design work to integrate.
• Predictable performance: Since they are implemented at the physical level, hard IPs deliver reliable and specific chip performance.

Soft IP cores

As a dynamic alternative, soft IP cores provide configurable options, offering enhanced flexibility and adaptability. Common soft IP cores include synthesizable RTL designs for digital blocks, configurable analog IP, and processor cores engineered for synthesis into the target technology.

Features of soft IP cores:

• Configurability: Soft IPs offer SoC design engineers’ greater freedom during the design exploration and optimization phases. They operate at a higher abstraction level, making them modifiable to meet specific application needs.
• Flexibility: These cores are technology-independent and can be synthesized and adapted for diverse process technologies.

Figure 3. Hard vs. soft core differences

Different semiconductor IP sources

Semiconductor IP can come from two major sources: third-party or in-house development teams.

Definition of third-party IP

A third-party silicon IP is licensed from an external vendor, enabling IC designers to access diverse functionalities without needing to design them from scratch. Acquiring third-party IP typically involves licensing agreements and royalty payments, which can impact project costs and intellectual property ownership. For such IPs, the organization must track and maintain business aspects of the vendor relationship, the vendor’s supply chain (for regulatory and security reasons), the costs at scale, and the licensing terms and conditions.

Definition of internal IP

Internal groups develop semiconductor IP cores for customization and specific design needs. Internally developed IP requires thorough verification and validation processes to ensure functionality, reliability, and compatibility with other system components. The design team must ensure ongoing maintenance and support, including updates for smaller process nodes or design revisions.

Main IP category by functionality

Semiconductor IP can also be categorized by key functionalities, facilitating efficient discovery and selection.

These categories include:

• Processor IP: These are cores of central processing units (CPUs) and accelerators, ranging from simple microcontrollers to complex multi-core processors.
• Memory IP: Memory systems such as SRAM (Static Random-Access Memory), DRAM (Dynamic RAM), Flash, and ROM (Read-Only Memory) store data and instructions within an IC.
• Analog and mixed-signal IP: These IP cores facilitate the processing of analog signals, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), analog filters, PLLs (Phase-Locked Loops), SerDes, and power management.
• Interface IP: These IP cores enable communication between different components within an IC or between ICs, including USB, PCIe, HDMI (High-Definition Multimedia Interface), Ethernet, and other standard interfaces.
• Security IP: Security IP cores are designed for hardware-level encryption, authentication, and other security functionalities to protect ICs from unauthorized access or attack
• Verification IP (VIP): VIPs are pre-designed verification components and test benches that validate the functionality and performance of IP cores and designs. They might include a set of assertions for verifying bus protocols or a module intended to be used within a defined verification methodology. Examples of VIP include FEC, CRC, UCIe1.2, and USBV4.
• RF (Radio Frequency) IP: These cores add RF functionality into the SoC design, including transmitter, receivers, synthesizers, low-noise amplifiers, and power amplifiers.

Each of these categories serves a specific function in the complex ecosystem of semiconductor design. IP management software such as Keysight HUB helps designers efficiently navigate through IP catalogs, identify relevant cores for their projects, and maximize reuse.

Figure 4. Market share of semiconductor IP by end users in 2023

Classifying IP by development methodology

While one primary way of classifying IP is by functionality, Keysight presents a new dimension of classification: development methodology.

With a more in-depth understanding of IP-driven design methodology, development teams can gain more insights into design strategies and optimization of development resources.

Figure 5. IP taxonomy based on development methodologies

Third-party IP

Companies increasingly turn to third-party IP vendors for various high-quality prebuilt components to accelerate design cycles and enhance productivity. Common examples of third-party IPs include CPU cores, memory units, and accelerators, which play pivotal roles in modern chip design. However, it is also essential to consider the basic building blocks of a chip, such as PDKs, primitive libraries, standard cells, and application-specific integrated circuit (ASIC) libraries. Evaluating these essential building blocks not only in terms of their technical merits (e.g., optimized power and area in the final design) but also through non-technical metrics (e.g., the effort required to integrate) provides invaluable insights for future project planning. At an organizational level, the IP procurement teams need to track business aspects of third-party IPs. When selecting a third-party IP, weighing not just the technical and operational merits but also the business implications is essential. Factors such as the business relationship with IP vendors, the cost implications of purchasing IPs at scale, and the licensing agreements for using IPs in specific applications are all critical considerations. By marrying the technical evaluation of the IP with robust business analysis, the procurement teams could make informed decisions that ensure the third-party IPs align with their strategic goals and design requirements.

Corporate IP

In the fast-paced semiconductor design sector, corporate intellectual property (IP) is a pivotal element for product differentiation. This often involves directly applying released versions of IP “as-is.” To cultivate such corporate IP, semiconductor companies either acquire smaller IP firms or mandate the organic growth of specialized teams for their niche expertise.

These specialized units often serve as internal service providers to other product teams involved in system-on-chip (SoC) design, playing a crucial role in the company’s innovation efforts. From operational and technical perspectives, these internal teams function equivalently to third-party IP vendors, albeit without the complexities associated with third-party business management. The Electronic Design Automation (EDA) team is a common yet frequently overlooked example. The EDA team manages process design kits (PDKs) by interfacing with foundries and modeling customization in medium to large semiconductor firms. Adopting the operational efficiency and mindset of third-party IP vendors is essential for these specialized teams to fully leverage their role in the corporate IP strategy. This involves meticulously tracking their internal customers, the specific IP releases each team utilizes, and any issues identified in customer projects throughout the IP lifecycle. Implementing a streamlined release methodology and leveraging tracked data for planning future modifications are critical steps toward enhancing efficient and productive corporate IP reuse.

Community IP enables effective IP reuse strategies, so design teams can leverage trusted IP sources from previously successful design projects. If a community IP has worked before, all that is needed is to verify it under the new project requirements.

A case in point is the phase-locked loop (PLL) IP, often used across chip designs for various applications within an organization. However, the specifications and requirements for the PLL differ from one project to the next. Instead of initiating each PLL design anew, engineering teams are inclined to modify or enhance the functionality and performance of an already successfully designed PLL to meet the needs of new applications. The reuse of PLL IP not only dramatically shortens the design cycle but also lowers overall development costs.

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What is IP reuse

Semiconductor IP reuse is an essential strategy in SoC (System on Chip) design, becoming increasingly relevant as more system companies choose to develop substantial components internally. This approach centers on using pre-existing, validated semiconductor Intellectual Property (IP) cores or design blocks in new projects, which streamlines the design process by avoiding the need to develop new IPs from scratch.

Key benefits of IP reuse in semiconductor design

• Faster design cycles: Reusing IP can drastically cut down development time, allowing designers to allocate resources to other critical aspects of SoC design.
• Enhanced product differentiation: IP reuse can free engineers’ time to concentrate on developing higher-level, innovative rather than foundational functions.
• Reduced costs and risks: By utilizing pre-tested IP blocks, companies can lower both the financial expenditures and the risks associated with performance flaws in modern designs.

What is a semiconductor IP lifecycle

A semiconductor IP lifecycle describes the stages of a silicon IP core from creation to decommissioning. Understanding the IP lifecycle is critical to effectively managing the complexities of System-on-Chip (SoC) designs and ensuring the IPs serve their purpose.

1. Identification: Design teams identify the specific IP requirements for an SoC. Based on the necessary functionalities, the team decides whether to develop or reuse in-house IP, license from third-party vendors, or tap into open-source IP.
2. Development: Whether acquired or developed in-house, the IP undergoes rigorous development, verification, and quality control processes to meet industry standards and design requirements.
3. Integration: Once the silicon IP is verified, it is cataloged in the organization’s design libraries. SoC developers then select and integrate it into the system architecture and connect it with other components, ensuring compatibility and functionality.
4. Verification: Design engineers ensure that the integrated IP cores meet stringent functional, performance, and reliability requirements through extensive testing and simulation methodologies.
5. Deployment: After successful verification, the SoC design moves into the fabrication process for physical chips.
6. Version control: Over time, the IP cores may undergo optimization including updates for new process nodes, bug fixes, and performance enhancements. Effective version control ensures that designers use the right version of each IP.
7. Tracking: Effective management of semiconductor IP involves tracking its usage across various projects, managing dependencies, updating its bill of material (BoM), and maintaining traceability to comply with regulatory requirements.
8. Decommission: As new standards and requirements emerge, older IP cores become obsolete. However, their documentation may still need to be maintained to meet an older chip’s contractual and regulatory obligations.

Figure 6. A semiconductor IP lifecycle

The semiconductor IP lifecycle highlights the need for robust management strategies that view IPs not just as individual components within an SoC but as integral parts of a larger ecosystem. IP management must extend beyond mere component-level tracking and encompass the broader ecosystem of SoC design.

Key IP management challenges

The ever-evolving landscape of integrated circuit (IC) design necessitates rigorous IP management strategies to optimize efficiency and mitigate risks. Here are some of the key challenges that industry professionals face.

Selecting suitable IP

Selecting the right IP cores is crucial yet time-consuming. It requires a thorough evaluation of a project’s design specifications, IP quality, licensing, and performance benchmarks. This process often involves dealing with various IP vendors at the engineering, business, and legal levels. It becomes more challenging to keep distributed teams aligned on IP consumption and share IP knowledge across disparate systems.

Integrating IP

Integrating heterogeneous in-house and third-party IP cores often takes significant engineering efforts to ensure performance, reliability, and compatibility in an application-specific way. Any incompatibility issues can delay project timelines and increase costs.

Verifying IP

Extensive simulations and rigorous verification are necessary to ensure that the integrated IP blocks function as expected. Detailed records of the entire verification process must be maintained for internal and regulatory accountability.

Tracking IP

Organizations must clearly track version changes, IP publishing and integration efforts, and licensing terms to avoid violations and ensure compliance with standards such as ISO 26262 functional safety requirements. However, the fragmentation of IP information across different systems and the lack of automated tracking poses a significant challenge to proving compliance throughout the engineering lifecycle.

Ensuring compliance

As IC designs become more complex, adhering to stricter industry standards becomes more challenging. Robust traceability across the design hierarchy is essential to meeting industry standards and governmental regulations, such as ITAR (International Traffic in Arms Regulations) and ISO 26262. This requires the SoC developers to collect and document evidence of compliance during the design process. Central IP management platforms that can automate this process and enhance IP traceability.

Securing IP

Maintaining the security of Intellectual Property (IP) is vital for preserving business competitiveness and adhering to stringent industry standards and regulations such as the Export Administration Regulations (EAR) and the International Traffic in Arms Regulations (ITAR). Risks of IP leakage—whether through unauthorized exports, ITAR disclosures, or exposure of confidential information—can lead to severe legal penalties.

To mitigate these risks, companies must implement robust security measures such as encryption, strict access controls based on roles and geographies, and regular compliance audits to protect their valuable IP assets effectively.

Facilitating multi-site collaboration

With design teams often spread across different geographical locations, enabling multi-site collaboration and knowledge sharing is crucial. This requires seamless access to collective IP knowledge, sophisticated role-based permission controls, interconnected data flows across various design tools, and cost-effective network storage strategies.

Five best practices for effective semiconductor IP management

To optimize semiconductor Intellectual Property (IP) management, it is imperative to implement the following best practices.

Centralizing IP catalog

Establishing a single source of truth for all design data and IP is pivotal for streamlining the integration processes and facilitating IP reuse.

Automating IP tracking

Automated IP tracking across projects eliminates the common pitfalls of fragmentation and enables visibility across the design hierarchy. Many industries have regulations that require IP traceability for functional safety. IP management software such as Keysight HUB helps streamline auditing and reporting to ensure that the product complies with these regulations.

Enhancing IP search

Equip your SoC developers with advanced search functionality that incorporates keywords, metadata, functionalities, process requirements, and licensing terms so they can swiftly identify and select the most effective IPs.

Integrating with existing workflows

Integrating the IP management system with existing electronic design automation (EDA) tools creates a robust framework for tracking and managing IPs throughout the design process. This integration ensures continuity and reliability, vital for maintaining project timelines and quality standards.

Enhancing IP security

Choosing an IP management system with stringent security measures, such as sophisticated access controls, automated revocation of permissions, and thorough auditing capabilities, is essential. These features safeguard sensitive IP against unauthorized access and potential breaches, securing your IP against internal and external threats.

IP management for chiplet-based designs

In this section, we analyze various aspects of semiconductor IP management specifically for chiplet-based designs.

Chiplets are small, modular, reusable ICs that are designed to be integrated into a larger SoC. They don’t need to be built on the same silicon die like traditional SoC designs. Instead, each chiplet can be built using a customized process node specifically optimized for its function and performance. Chiplets communicate through high-speed interconnect technologies like the Universal Chiplet Interconnect Express.

Figure 7. IP management for migrating from SoC to chiplet designs

Chiplet-based designs enable the use of highly optimized process nodes and other technologies for every chiplet. The potential benefits include more design flexibility, enhanced performance, and cost savings by using stable process nodes for most chiplets and advanced nodes only for a few.

Key IP management considerations for chiplets

Chiplet-based designs also involve unique considerations and challenges in IP management workflows, ranging from packaging, and interconnect models to verification traceability. Before migrating from SoC to chiplet-based designs, new infrastructure and tools to support the IP / design ecosystem are needed.

IP selection

As designs grow more heterogenous, selecting suitable chiplet IPs is more complex. They must be compatible when sourced from different vendors or fabricated with different process technologies.

Figure 8. Keysight HUB enabling easy IP selectio n

IP integration

Selected IPs must integrate seamlessly and function correctly with each other. Their interfaces need careful analysis to ensure high performance and reliable communication, even if their process nodes or sources are different.

Verification

Individual functionalities and their interactions must be verified. Building and retaining reliable organizational knowledge about chiplet compatibility is essential, especially if a lot of third-party chiplet IPs are used.

Compliance

The integrated assembly must comply with industry standards — like the International Organization for Standardization (ISO) 26262 for automotive functional safety — as well as export regulations. The integration must fully comply with every chiplet IP’s licensing terms.

Security

An integrated design of many chiplets is a larger attack surface compared to a monolithic design, requiring careful analysis of vulnerabilities and cybersecurity measures against them.

Tracking

Dependency management and traceability are crucial in chiplet-based designs. It is vital to accurately track all the dependencies among various IPs used across chiplets to efficiently manage updates, modifications, or substitutions.

Future trends in semiconductor IP management

There are three emerging trends shaping the semiconductor IP management strategies.

No. 1 Demand for effective semiconductor IP management

The growing complexity of chips coupled with fast time-to-market demands have necessitated the outsourcing of most IP cores to specialist vendors. Powerful IP management solutions are essential to manage this level of third-party IP reuse.

No. 2 Increased use of open-source IP cores

Open-source IP cores like the reduced instruction set computer (RISC-V) architecture are becoming more popular because of their royalty-free open-source licenses, which enable deep customization at low costs.

No.3 Need for more IP security

Chips are critical components in multiple business verticals as well as defense and space equipment. As geopolitical tensions grow around the world, the semiconductor industry is increasingly seen as a strategic advantage. Governments have started scrutinizing IP security and confidentiality aspects more stringently.

Transform your semiconductor IP management with Keysight’s powerful solutions

Keysight IP Management (HUB) is a powerful enterprise-grade semiconductor IP management solution that follows all the best practices we outlined earlier. Formerly known as Cliosoft HUB, this ISO 26262-certified platform enables enterprise-wide IP catalog and IP reuse, design traceability for complete management control, and comprehensive collaboration support. It integrates IP management, design data management, traceability, and change management workflows with popular design tools like Cadence Virtuoso Studio, Siemens EDA (Pyxis), and Keysight ADS (Advanced Design System).

How Keysight IP Management (HUB) can help

• IP designers can seamlessly create, manage, and share IP, while improving comprehension and enabling reuse.
• IP consumers have full visibility into all the IP available across the enterprise, including both internal and third-party versions.
• SoC designers and managers gain clear IP traceability across the full design hierarchy, with access to change reviews, conflict analysis, and release approvals.

Claim your free trial to see how Keysight HUB helps optimize your company’s semiconductor IP management practices.