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Optimizing IC Design Data Management: Git-R-Don’t for Hardware Design


Git is an important distributed version control system designed for software engineers. It preserves a comprehensive history of changes and provides advanced operations for efficient project management. This feature makes Git an ideal tool for software development, enabling teams to house an entire project within a single repository.

However, adapting Git for hardware design poses distinct challenges, as the data requirements and workflows significantly differ from software development.

Silicon Valley venture capitalist Marc Andreessen proclaimed, “Software is eating the world” in 2011. Software complexity has continuously escalated, necessitating more iterations, managing larger files, collaboration across global teams, and storing a higher data volume.

Initially, version control tools like RCS and SCCS provided basic revision management for individual files. They store the code base history on the same disk storage used for the code under development. As a result, those initial version control tools fell short in handling the entire software project. This gap led to wrappers such as Concurrent Versions System (CVS) in 1986.

As software development extended to geographically distributed workforces and needed more sophisticated configuration management, client-server systems like SVN, ClearCase, and Perforce became popular around the early 90s. These systems emerged as a user-friendly successor to CVS, offering a centralized repository for managing file versions and facilitating collaboration among developers. Over time, it gained widespread adoption for its simplicity and branching capabilities.

With the growth of the open-source Linux Kernel, the Linux community built its own version control tool, Git, in 2005 to handle the distributed development of large open-source projects. Git, a distributed version control system, rose to prominence as a faster, more flexible alternative to SVN. Its decentralized approach and powerful branching features empowered developers and revolutionized software development workflows.

Challenges of Configuration Management in Semiconductor Engineering

With today’s semiconductor design scales to a team of thousands of engineers, configuration management challenges extend beyond software development. Fields such as integrated circuit (IC) design and semiconductor engineering confront similar challenges, including:

  • Managing multiple iterations.
  • Storing many sizable files of different types
  • Collaborating with multiple cross-functional geodiversity teams.

Accurately tracking revisions and configurations is crucial in these contexts, highlighting the need for efficient version control systems tailored for hardware engineers.

But what is an ideal version control solution for managing projects in IC design domains and workflows?

Semiconductor Design vs. Software Development: What Is the Difference?

Semiconductor design and software projects share common ground.

First, both involve extensive collaboration among multiple engineers who create, debug, and refine many files across multiple iterations. This process necessitates a seamless solution for team members to exchange updates, including creating release candidates and base variants as the project progresses.

Despite these similarities, semiconductor design diverges significantly in its data type, workflows, and requirements.

Data types

Digital designs are typically done using text files written in Register Transfer Level (RTL) language, such as Verilog. Their management is similar to software version controls systems. However, there are other analog, custom, and packaging components and specialized graphical tools (known as Electronic Design Automation or EDA tools), like schematic and layout editors. These EDA tools produce a suite of related files, often encompassing large binary files to represent design objects that need to be verified by multiple EDA toolchains and flows, marking a clear departure from the typical software development workflow of editing, compiling, and debugging.

Workflows

The semiconductor design flow introduces a higher level of complexity, incorporating various stages such as synthesis, placement and routing, simulations of analog and digital components, formal verification, physical verification, and timing analysis. Each stage requires specific expertise and human intervention to interpret the results. Such as flow generates a significant amount of, often binary files and co-managed files (multiple files that should be viewed as a single design object) necessitating not just the traditional meticulous version control but also stringent configuration management.

In comparison, a software workflow involves a much well-defined linear loop of edit, compile, test, and debug flow.

Execution

Throughout the IC design flow, some components may be reusable in whole or in part, typically referred to as Intellectual Property (IP) blocks. Companies either develop IP internally or procure it from third-party vendors such as Arm and Synopsys. Semiconductor IP is the fundamental functional block for today’s SoC or chiplet designs. Effective IP management demands not only an accessible IP catalog but also advanced revision control, access control, and traceability across design hierarchies.

Git works very well for managing software development, with each engineer working on developing a feature or fixing issues. Its powerful ability to merge changes to text files enables truly efficient distributed development, especially for open-source projects. However, does Git meet the requirements of semiconductor design?

Six Challenges of Using Git for IC Design Data Management

No.1 Handling large files

IC design has exceptionally large files from hundreds of megabytes to gigabytes. The Git’s model requires users to clone the repository. As a result, every IC designer on the project needs to create a copy of all the large design files and all the revisions. This approach becomes impractical due to the storage implications, especially when considering the costs of high-availability network storage in a corporate setting.

file sizes for MMIC, Analog, PDK, digital design
Figure 1. IC design sizes

No. 2 Binary file management

The inability to automate merging for schematics and layouts needs a centralized repository to prevent manual merging errors due to accidental overwrites. Also, engineers need a locking mechanism to ensure that fellow engineers are not making changes to the same file at the same time to enhance collaboration and efficiency.

No. 3 Geographical distribution

Design teams are often geographically distributed. The teams need to synchronize their changes daily or more often. Technology such as cache servers is necessary to make this more efficient especially given the size of the design data.

No. 4 Access control

As design objects are often stored as a collection of co-managed files, a configuration management system should recognize these as related and manage it as a single, user recognizable, composite design object.

Individual engineers or contractors have different responsibilities in the same design project, requiring the system to have proper access controls in place. For instance, you may want to make sure that a layout engineer doesn’t change a schematic design. You may also want to prevent contractors from having any access to sensitive libraries. To enforce access controls, you need to have project data managed by a centralized server.

No.5 Design hierarchy management

Unlike software development, where data is often organized in a simple flat directory structure, IC (Integrated Circuit) design involves a complex hierarchy of blocks. Each level of this hierarchy relies on integrating a lower-level block, making the organizational structure critical for IC designers. To manage these intricate designs, IC designers require a robust configuration management system capable of handling and executing within this hierarchical framework. Imagine the challenges software developers would face without the ability to compare different versions of their files to spot changes. Such a scenario would make it extremely difficult to review modifications or pinpoint the source of new bugs. Similarly, IC designers and layout engineers should have access to advanced tools that enable them to detect differences between versions of schematics or layouts.

No.6 Design tool Integration

The most challenging requirement for IC design data management is that revision control and configuration management features must seamlessly integrate into the design tools. In addition to efficient processes, design tools must be aware of the configuration management system to make sure that design changes are correctly recorded and trackable.

Streamline IC Design Data Management with Keysight SOS

There’s often a strong temptation to look for tools that already exist and shoehorn them to meet similar needs in a different domain. However, while Git and other software configuration management (SCM) tools fit well with software development, they fall short in specific requirements of IC design, from binary file management to design tool integration.

Keysight Design Data Management (SOS) is a system designed from the ground up to meet the unique requirements of semiconductor IC designers.

Keysight SOS can recognize composite design objects, understand IC design hierarchy, and reduce network storage through smart cache. Most importantly it has seamless integration with all major EDA (Electronic Design Automation) tools including Cadence Virtuoso Studio, Synopsys Custom Compiler, Keysight ADS (Advanced Design System), and more.

Keysight SOS, data managmenet for Cadence Virtuoso
Figure 2. Keysight SOS partners with all major EDA vendors

Get a free trial of Keysight Design Data Management (SOS) to see how it can elevate your team’s design reuse efficiency and streamline design data flow from concept to tape-out.



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